1. Field of the Invention
The present invention relates to a charging circuit and a semiconductor memory device using the charging circuit, and in particular, to a charging circuit for charging a load circuit to a prescribed voltage level, and a semiconductor memory device for charging a bit line using the charging circuit.
2. Description of the Related Art
A semiconductor memory device includes a plurality of memory cells arranged in a matrix. Before reading information stored in one of the memory cells or writing information to one of the memory cells, a bit line connected to the memory cell needs to be charged. In the case of a nonvolatile semiconductor memory device, the charging operation is performed in order to raise the speed of reading the information from the memory cell. In the case of a volatile semiconductor memory device, the charging operation is performed in order to prevent inadvertent overwriting of the information stored in the memory cell when reading the information.
FIG. 7 shows an exemplary charging circuit 700 which is conventionally and generally used in a single bit semiconductor memory device. The charging circuit 700 includes three N-type MOS transistors NO, N1 and N2. A drain of the N-type MOS transistor N1 is connected to a power supply VCC via a resistor R1, and a source of the N-type MOS transistor N1 is connected to ground VSS. A gate of the N-type MOS transistor N1 is connected to a source of the N-type MOS transistor N2. A gate of the N-type MOS transistor N2 is connected to a node 23 between the drain of the N-type MOS transistor N1 and the resistor R1. A drain of the N-type MOS transistor N2 is connected to the power supply VCC. The gate of the N-type MOS transistor N2 is connected to a gate of the N-type MOS transistor N0, and the source of the N-type MOS transistor N2 is connected to a source of the N-type MOS transistor N0. The source of the N-type MOS transistor N0 is also connected to an output node VPR, which is an output terminal of the charging circuit 700. A drain of the N-type MOS transistor N0 is connected to the power supply VCC via a resistor R0. A node 22 between the drain of the N-type MOS transistor N0 and the resistor R0 is connected to a sense amplifier (not shown).
In the charging circuit 700, a load circuit to be charged (not shown) is connected to the output node VPR. The node 22 connected to the drain of the N-type MOS transistor N0 conveys a change in the level of the charging current, which is output from the output node VPR, to the sense amplifier as a change in the voltage. An inverter, including the N-type MOS transistor N1 and the resistor R1, detects the voltage level of the output node VPR from the gate of the N-type MOS transistor N1. Then, the inverter feeds back the voltage level of the output node VPR via the node 23, connected to the drain of the N-type MOS transistor N1, to the gate of the N-type MOS transistor N2 and to the gate of the N-type MOS transistor N0. Thus, the charging operation performed via the output node VPR and the operation of the sense amplifier are improved in speed.
FIG. 8 shows an exemplary charging circuit used for a semiconductor memory device including a pair of complementary bit lines (a bit line BIT and a bit line /BIT having a logic level inverted from the logic level of the bit line BIT). In FIG. 8, a power supply VM is a power supply or an output terminal of an internal voltage drop circuit.
The charging circuit 800 includes an N-type MOS transistor N3 between the power supply VM and the bit line BIT and an N-type MOS transistor N4 between the power supply VM and the bit line /BIT. The N-type MOS transistors N3 and N4 are load transistors. An N-type MOS transistor NEQ for equalizing the bit lines is provided between the bit lines BIT and /BIT (i.e., for charging the bit lines BIT and /BIT to an equal potential). In the case where a withstand voltage of the memory cell (not shown) connected to the bit lines BIT and /BIT is lower than the external supply voltage, the output terminal of the internal voltage drop circuit is used as the power supply VM.
Drains of the N-type MOS transistor N3 and N4 are connected to the power supply VM. A source of the N-type MOS transistor N3 is connected to the bit line BIT, and a source of the N-type MOS transistor N4 is connected to the bit line /BIT. Gates of the N-type MOS transistors N3 and N4 are connected to each other. A drain and a source of the N-type MOS transistor NEQ are respectively connected to the source of the N-type MOS transistor N3 and the source of the N-type MOS transistor N4. A gate of the N-type MOS transistor NKQ is connected to the gates of the N-type MOS transistors N3 and N4.
The N-type MOS transistor NEQ is connected to the bit lines BIT and /BIT so as to equalize the bit lines BIT and /BIT. The gate of the N-type MOS transistor NEQ receives an equalizing signal EQ1. The equalizing signal EQ1 is also input to the gates of the N-type MOS transistors N3 and N4.
While the equalizing signal EQ1 is at a HIGH logic level, the N-type MOS transistors N3, N4 and NEQ are all in an ON state. The source and the drain of the N-type MOS transistor N3 are conductive with each other, and the source and the drain of the N-type MOS transistor N4 are conductive with each other. Therefore, the voltage of the power supply VM is applied to the bit lines BIT and /BIT. Since the drain and the source of the N-type MOS transistor NBQ are also conductive with each other, the equalization operation is performed for charging the bit lines BIT and /BIT to an equal potential.
As a result, while the equalizing signal EQ1 is at a HIGH logic level, the voltage of the power supply VM is supplied to the memory connected to the bit lines BIT and /BIT.
As described above, the charging circuit 800 uses N-type MOS transistors. The threshold voltage drop function of the N-type MOS transistors is utilized to pre-charge the bit lines BIT and /BIT to 1/2 VCC. This provides the effect of reducing power consumption and noise while charging and discharging the bit lines BIT and /BIT.
A conventional single bit semiconductor memory device uses the charging circuit 700 shown in FIG. 7 so as to charge the bit line utilizing a voltage drop corresponding to the threshold voltage Vth of the N-type MOS transistors. A semiconductor memory device integrally including an internal voltage drop circuit uses the charging circuit 800 shown in FIG. 8. The complementary bit lines BIT and /BIT connected to all the memory cells are charged, using the voltage of the output terminal VM of the internal voltage drop circuit as the power supply voltage of the N-type MOS transistors.
The charging circuit 700 has the following problem. As the potential of the sources of the N-type MOS transistors increases during the charging operation, the difference in potential between the gate and the source of each N-type MOS transistor is reduced. This is accompanied by reduction in the driving capability of the N-type MOS transistors, which inevitably increases the charging time period.
The charging circuit 800 has the following problem. The load on the internal voltage drop circuit for supplying a voltage for charging is excessively high. Accordingly, an excessively large output capacity is required in order to obtain stable operation.
According to one aspect of the invention, a charging circuit for charging a prescribed load circuit to a prescribed potential includes a charging driving circuit connected to the load circuit for supplying a charging signal to the load circuit from an output end of the charging driving circuit; a time constant circuit for receiving the charging signal, changing a time constant of the charging signal and outputting a transition signal having a prescribed transition time period; a control circuit for outputting a control signal for setting a time constant of the time constant circuit in accordance with the prescribed load circuit; a voltage detection circuit for detecting that the transition signal output from the time constant circuit has reached the prescribed potential and outputting a detection signal; and a delay and inversion circuit for delaying, and inverting a logic level of, an externally input charging control signal, and outputting a delay signal. The charging driving circuit starts a charging operation in accordance with the delay signal output from the delay and inversion circuit, and terminates the charging operation in accordance with the detection signal output from the voltage detection circuit.
In one embodiment of the invention, the output end is grounded by the delay signal during a delay time period from the time when the charging control signal is input to the delay and inversion circuit until the time when the delay signal is output.
In one embodiment of the invention, an output section of the voltage detection circuit is a transfer gate which becomes conductive when the delay signal is placed into an active state. The transfer gate is connected to a gate of a P-type MOS transistor of the charging driving circuit. The gate of the P-type MOS transistor is connected to a pull-up circuit for placing the P-type MOS transistor into a non-conductive state when the delay signal is placed into an inactive state.
In one embodiment of the invention, the time constant circuit includes a plurality of P-type MOS transistors connected in series, and a plurality of N-type MOS transistors each having a source connected to a source of a respective P-type MOS transistor and a drain connected to a drain of the respective P-type MOS transistor. A gate of each of the plurality of P-type MOS transistors is connected to the ground. A well region of each gate is connected to a prescribed internal power supply of the charging circuit. A gate of each of the plurality of N-type MOS transistors receives a control signal output from the control circuit.
In one embodiment of the invention, an ON resistance of each of the plurality of N-type MOS transistors is set to be smaller than an ON resistance of each of the plurality of P-type MOS transistors.
According to another aspect of the invention, a semiconductor memory device includes the above-described charging circuit; a pair of complementary bit lines connected to a memory cell; and an equalizing circuit for equalizing the pair of complementary bit lines to an equal prescribed potential using an equalizing signal acting as a charging control signal. An output end of the charging driving circuit of the charging circuit is connected to the pair of complementary bit lines.
In one embodiment of the invention, the semiconductor memory device includes at least one more pair of complementary bit lines, wherein the output end of the charging driving circuit of the charging circuit is connected to the pairs of complementary bit lines.
In one embodiment of the invention, the equalizing circuit includes a pull-up circuit for charging the pair of complementary bit lines to a prescribed potential.
In one embodiment of the invention, the equalizing circuit includes a pull-up circuit for charging the pair of complementary bit lines to a prescribed potential, and the delay and inversion circuit of the charging circuit provides a delay time period which is at least equal to a time period required for the pair of complementary bit lines, charged to the prescribed potential by the pull-up circuit, to be discharged via the output end of the charging driving circuit.
In one embodiment of the invention, the delay and inversion circuit of the charging circuit provides a delay time period which is at least equal to a time period required for the pair of complementary bit lines, charged to the prescribed potential by the pull-up circuit, to be discharged via the output end of the charging driving circuit.
Thus, the invention described herein makes possible the advantages of providing a charging circuit for performing a stable charging operation at high speed without deteriorating the driving characteristics of MOS transistors included therein, and a semiconductor memory device using the same.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.